Thin film transistor array substrate and method of fabricating the same

ABSTRACT

A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.

The present invention claims the benefit of Korean Patent ApplicationNos. P2003-70836 and P2003-90285, filed in Korea on Oct. 11, 2003 andDec. 11, 2003, respectively, which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an array substrate and a method offabricating an array substrate, and more particularly, to a thin filmtransistor (TFT) array substrate and a method of fabricating a TFT arraysubstrate.

2. Description of the Related Art

In general, a liquid crystal display (LCD) device produces an image byadjusting light transmittance of a liquid crystal material using anelectric field. The LCD device includes an LCD panel in which liquidcrystal cells are arranged in a matrix configuration, and a drivingcircuit for driving the LCD panel.

The LCD panel includes a TFT array substrate and a color filter (CF)array substrate that face each other, wherein a spacer is located formaintaining a uniform cell gap between the TFT and CF array substratesand a liquid crystal material is provided within the cell gap.

The TFT array substrate includes gate lines and data lines, a TFT formedas a switching device at each intersection of the gate and data lines, apixel electrode connected to the TFT formed for each of a plurality ofliquid crystal cells, and an alignment film applied to each of theliquid crystal cells. The gate lines and the data lines receive signalsfrom the driving circuits through corresponding pad portions.Accordingly, the TFT, in response to a scan signal supplied to a gateline, supplies a pixel voltage signal transmitted along a data line tothe pixel electrode.

The CF array substrate includes a color filter formed by the liquidcrystal cell, a black matrix that reflects external light and separateseach of the color filters, a common electrode commonly supplying areference voltage to the liquid crystal cells, and an alignment filmdisposed on each of the liquid crystal cells.

The LCD panel is fabricated by combining the TFT array substrate and theCF array substrate that have been separately manufactured, injecting theliquid crystal material between the TFT and CF array substrates andsealing the TFT and CF array substrates together with the liquid crystalmaterial therebetween.

In the LCD device, since fabrication of the TFT array substrate involvessemiconductor processing including a plurality of individual maskprocesses, the fabrication process for the TFT array substrate iscomplicated and is a major cost factor in the fabrication costs of theLCD panel. Thus, fabrication of the TFT array substrate has beendeveloped in order to reduce the number of individual mask processes.For example, one mask process includes multiple individual processes,such as thin film deposition, cleaning, photolithography, etching,photo-resist stripping, and inspection processes. Presently, four-roundmask processes have been developed, wherein one mask process is reducedfrom an existing five-round mask process that is employed as a standardmask process.

FIG. 1 is a plan view of a TFT array substrate according to the relatedart, and FIG. 2 is a cross sectional view along I-I′ of FIG. 1 accordingto the related art. In FIGS. 1 and 2, a TFT array substrate includesgate lines 2 and data lines 4 crossing each other and having a gateinsulating film 44 therebetween on a lower substrate 42, a TFT 6 formedat each crossing of the gate and data lines 2 and 4, and a pixelelectrode 18 formed in a cell region arranged by the crossing of thegate and data lines 2 and 4. In addition, the TFT array substrateincludes a storage capacitor 20 formed at an overlapped part of thepixel electrode 18 and a pre-stage gate line 2, a gate pad part 26connected to the gate line 2, and a data pad part 34 connected to thedata line 4.

The TFT 6 includes a gate electrode 8 connected to the gate line 2, asource electrode 10 connected to the data line 4, a drain electrode 12connected to a pixel electrode 18, and an active layer 14 ofsemiconductor pattern 47 defining a channel between the source electrode10 and the drain electrode 12 and overlapping the gate electrode 8. Theactive layer 14 overlaps a lower data pad electrode 36, a storageelectrode 22, the data line 4, the source electrode 10, and the drainelectrode 12, and includes a channel portion defined between the sourceelectrode 10 and the drain electrode 12. In addition, an ohmic contactlayer 48 of the semiconductor pattern 47 is used for making an ohmiccontact with the lower data pad electrode 36, the storage electrode 22,the data line 4, the source electrode 10, and the drain electrode 12,and is further formed on the active layer 14. The TFT 6, in response tothe gate signal supplied to the gate line 2, causes a pixel voltagesignal supplied to the data line 4 to be charged to and maintained inthe pixel electrode 18.

In FIG. 2, the pixel electrode 18 is connected to the drain electrode 12of the TFT 6 via a first contact hole 16 passing through a passivationfilm 50. The pixel electrode 18 generates a potential difference alongwith the common electrode formed on an upper substrate (not shown) by acharged pixel voltage. Due to the potential difference, the liquidcrystal material located between the TFT substrate and the uppersubstrate (not shown) rotates due to a dielectric anisotropy of theliquid crystal material, and transmits incident light through the pixelelectrode 18 from a light source (not shown) onto the upper substrate(not shown).

The storage capacitor 20 includes a pre-stage gate line 2, a storageelectrode 22 overlapping the pre-stage gate line 2 with the gateinsulating film 44, with the active layer 14 and the ohmic contact layer48 therebetween, and the pixel electrode 18 connected through a secondcontact hole 24 formed at the passivation film 50 and overlapped withthe storage electrode 22 having the passivation film 50 therebetween.The storage capacitor 20 stably maintains the pixel voltage charged tothe pixel electrode 18 until a subsequent pixel voltage is charged.

The gate line 2 is connected to a gate driver (not shown) through thegate pad part 26. The gate pad part 26 includes a lower gate padelectrode 28 extending from the gate line 2, and an upper gate padelectrode 32 connected to the lower gate pad electrode 28 via a thirdcontact hole 30 passing through both of the gate insulating film 44 andthe passivation film 50. The data line 4 is connected to a data driver(not shown) through the data pad part 34. The data pad part 34 includesthe lower data pad electrode 36 extending from the data line 4, and anupper data pad electrode 40 connected to the lower data pad electrode 36via a fourth contact hole 38 passing through the passivation film 50.

The TFT substrate having the above-described configuration is formedusing a four-round mask process.

FIGS. 3A to 3D are cross sectional views along I-I′ of FIG. 1 showing amethod of fabricating the TFT array substrate of FIG. 2 according to therelated art. In FIG. 3A, gate patterns are formed on the lower substrate42. On the lower substrate 42, a gate metal layer is formed by adeposition method, such as a sputtering. Subsequently, the gate metallayer is then patterned by photolithography using a first mask and anetching process to form the gate patterns including the gate line 2, thegate electrode 8, and the lower gate pad electrode 28. A material forthe gate metal layer includes chromium (Cr), molybdenum (Mo), aluminium(Al) and the like, which are used in a form of a single-layer structureor a double-layer structure.

In FIG. 3B, the gate insulating film 44, the active layer 14, the ohmiccontact layer 48, and source/drain patterns are sequentially formed onthe lower substrate 42 provided with the gate pattern. The gateinsulating film 44, an amorphous silicon layer, an n⁺ amorphous siliconlayer, and a source/drain metal layer are sequentially formed on thelower substrate 42 having the gate patterns thereon by a depositiontechnique, such as plasma enhanced chemical vapor deposition (PECVD) andsputtering.

For example, a photo-resist pattern is formed on the source/drain metallayer by a photolithography process using a second mask. The second maskemploys a diffractive exposure mask having a diffractive exposing part,wherein the diffractive exposing part corresponds to a channel portionof the TFT. As a result, a photo-resist pattern of the channel portionhas a lower height than a photo-resist pattern of the source/drainpattern part.

Subsequently, the source/drain metal layer is then patterned by a wetetching process using the photo-resist pattern to form source/drainpatterns including the data line 4, the source electrode 10, the drainelectrode 12, which is integral to the source electrode 10, and thestorage electrode 22.

Next, the amorphous silicon layer and the n⁺ amorphous silicon layer arepatterned at the same time by a dry etching process using the samephoto-resist pattern to form the semiconductor pattern 47 including theohmic contact layer 48 and the active layer 14.

The photo-resist pattern having a relatively low height in the channelportion is removed by an ashing process, and the source/drain patternand the ohmic contact layer 48 of the channel portion are etched by adry etching process. Accordingly, the active layer 14 of the channelportion is exposed to separate the source electrode 10 from the drainelectrode 12. Then, a remainder of the photo-resist pattern left on thesource/drain pattern is removed using a stripping process.

The gate insulating film 44 is made of an inorganic insulating material,such as silicon oxide (SiO_(x)) or silicon nitride (SiN_(x)). A metalfor the source/drain pattern includes molybdenum (Mo), titanium (Ti),tantalum (Ta), and Mo alloy or the like.

In FIG. 3C, the passivation film 50 including first, second, third, andfourth contact holes 16, 24, 30, and 38 are formed on the gateinsulating film 44 having the source/drain patterns. The passivationfilm 50 is entirely formed on the gate insulating film 44 having thesource/drain patterns by a deposition technique, such as a PECVD. Then,the passivation film 50 is patterned by photolithography using a thirdmask and an etching process to form the first, second, third, and fourthcontact holes 16, 24, 30, and 38. The first contact hole 16 is formed topass through the passivation film 50 and expose the drain electrode 12,whereas the second contact hole 24 is formed to pass through thepassivation film 50 and expose the storage electrode 22. The thirdcontact hole 30 is formed to pass through the passivation film 50 andthe gate insulating film 44 and expose the lower gate pad electrode 28.The fourth contact hole 38 is formed to pass through the passivationfilm 50 and expose the lower data pad electrode 36.

The passivation film 50 is made of an inorganic insulating material,such as a material of the gate insulating film 44 or of an organicinsulating material having a small dielectric constant, such as anacrylic organic compound, benzocyclobutene (BCB), orperfluorocyclobutane (PFCB).

In FIG. 3D, transparent electrode patterns are formed on the passivationfilm 50. For example, a transparent electrode material is entirelydeposited on the passivation film 50 by a deposition technique, such asa sputtering and the like. Then, the transparent electrode material ispatterned by photolithography using a fourth mask and an etching processto provide the transparent electrode patterns including the pixelelectrode 18, the upper gate pad electrode 32, and the upper data padelectrode 40. The pixel electrode 18 is electrically connected, via thefirst contact hole 16, to the drain electrode 12 while beingelectrically connected, via the second contact hole 24, to the storageelectrode 22 overlapping a pre-stage gate line 2. The upper gate padelectrode 32 is electrically connected, via the third contact hole 30,to the lower gate pad electrode 28. The upper data pad electrode 40 iselectrically connected, via the fourth contact hole 38, to the lowerdata pad electrode 36. Accordingly, the transparent electrode materialis made of an indium-tin-oxide (ITO), tin-oxide (TO), or anindium-zinc-oxide (IZO).

As described above, the TFT array substrate and the method offabricating the TFT array substrate uses a four-round mask process,thereby reducing the number of fabrication processes in comparison withthe five-round mask process and reducing fabrication costs. However,since the four-round mask process has a relatively complex fabricationprocess and reduction of the manufacturing costs is limited, furthersimplification of the fabrication process and further reduction of themanufacturing costs is required.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed toward a TFT arraysubstrate and method of fabricating a TFT array substrate thatsubstantially obviates one or more of the problems due to limitationsand disadvantages of the related art.

An object of the present invention is to provide a TFT array substratehaving a simplified structure.

Another object of the present invention is to provide a method offabricating a TFT array substrate having a simplified fabricationprocesses.

Another object of the present invention is to provide a TFT arraysubstrate having improved production yield and image quality.

Another object of the present invention is to provide a method offabricating a TFT array substrate having an improved production yieldand image quality.

Additional features and advantages of the invention will be set forth inthe description which follows, and in part will be apparent from thedescription, or may be learned by practice of the invention. Theobjectives and other advantages of the invention will be realized andattained by the structure particularly pointed out in the writtendescription and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purposeof the present invention, as embodied and broadly described, a thin filmtransistor array substrate device includes a gate line formed on asubstrate, a data line crossing the gate line with a gate insulatingpattern position therebetween, a thin film transistor at a crossing ofthe gate line and the data line, a pixel electrode formed at a pixelregion defined by the crossing of the gate line and the data line andconnected to the thin film transistor, a gate pad part having a lowergate pad electrode connected to the gate line and an upper gate padelectrode connected to the lower gate pad electrode, a data pad parthaving a lower data pad electrode connected to the date line and anupper data pad electrode connected to the lower data pad electrode, anda passivation film pattern formed at a region besides the regionincluding the pixel electrode, the upper data pad electrode, and theupper gate pad electrode, wherein the pixel electrode is formed on thegate insulating pattern of the pixel region exposed by the passivationfilm pattern.

In another aspect, a method of fabricating a thin film transistor arraysubstrate includes forming a gate pattern on a substrate, the gatepattern including a gate electrode of a thin film transistor, a gateline connected to the gate electrode, and a lower gate pad electrodeconnected to the gate line, forming a gate insulating film on thesubstrate having the gate pattern, forming a source/drain patternincluding a source electrode and a drain electrode of the thin filmtransistor, a data line connected to the source electrode and a lowerdata pad electrode connected to the data line, and a semiconductorpattern formed beneath the source/drain pattern there along, and forminga transparent electrode pattern and a passivation film pattern stackedon remaining areas except for areas at which the transparent electrodepattern is formed, wherein the transparent electrode pattern includes apixel electrode connected to the drain electrode and formed on the gateinsulating film, an upper gate pad electrode connected to the lower gatepad electrode, and an upper data pad electrode connected to the lowerdata pad electrode.

In another aspect, a method of fabricating a thin film transistorsubstrate includes preparing a transparent substrate, depositing a firstmetal film on the substrate and then forming a gate line, a gateelectrode and a gate pad through a first mask process, sequentiallystacking a fist insulating film, an amorphous silicon layer, an n⁺amorphous silicon layer and a second metal film on an entire surface ofthe substrate having the gate electrode and the gate line, and forming adata line vertically crossing the gate line and defining a pixel regiontogether with the gate line, a semiconductor layer having an activelayer and an ohmic contact layer, a source/drain electrode, and a datapad through a second mask process, and forming a second insulating filmon an entire surface of the substrate having the data line and thesource/drain electrode, exposing the first insulating film of the pixelregion, the gate pad and the data pad through a third mask process,depositing a transparent conductive film on an upper portion of thefirst insulating film, the gate pad and the data pad, to thereby form apixel electrode connected to the drain electrode, a gate connectionterminal connected to the gate pad, and a data connection terminalconnected to the data pad.

In another aspect, a method of fabricating a thin film transistor arraysubstrate includes preparing a transparent substrate, forming a gateline, a gate electrode, and a gate pad on the substrate, forming a gateinsulating film along an entire surface of the substrate having the gateelectrode and the gate pad, forming a data line to vertically cross thegate line and defining a pixel region together with the gate line, asemiconductor layer having an active layer and an ohmic contact layer, asource/drain electrode, and a data pad, exposing the gate insulatingfilm formed at each pixel region, forming a passivation film along anentire surface of the substrate having the data line and thesource/drain electrode, applying a photo-resist film to an upper portionof the passivation film, forming a photo-resist pattern on thepassivation film by using a mask, forming a contact hole exposing eachof the gate pad and the data pad by using the photo-resist pattern as amask for etching, and exposing the gate insulating film of the pixelregion, depositing a transparent conductive film along an entire surfaceof the substrate having the photo-resist pattern, the gate insulatingfilm of the pixel region and the contact hole, removing the photo-resistpattern and the transparent conductive film formed on the photo-resistpattern to form a pixel electrode on the gate insulating film of thepixel region, and forming a gate connection terminal and a dataconnection terminal respectively connected via the contact hole to thegate pad and the data pad.

It is to be understood that both the foregoing general description andthe follow detailed description are exemplary and explanatory and areintended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention andtogether with the description serve to explain the principles of theinvention. In the drawings:

FIG. 1 is a plan view of a TFT array substrate according to the relatedart;

FIG. 2 is a cross sectional view along I-I′ of FIG. 1 according to therelated art;

FIGS. 3A to 3D are cross sectional views along I-I′ of FIG. 1 showing amethod of fabricating the TFT array substrate of FIG. 2 according to therelated art;

FIG. 4 is a plan view of an exemplary TFT array substrate according tothe present invention;

FIG. 5 is a cross sectional view along II-II′ of FIG. 5 according to thepresent invention;

FIGS. 6A and 6B are plan and cross sectional views, respectively, of anexemplary first mask process of a method of fabricating a TFT arraysubstrate according to the present invention;

FIGS. 7A to 7C are a plan view and sectional views, respectively, of anexemplary second mask process of a method of fabricating a TFT arraysubstrate according to the present invention;

FIGS. 8A to 8D are a plan view and cross sectional views, respectively,of an exemplary third mask process of a method of fabricating a TFTarray substrate according to the present invention;

FIG. 9 is a plan view of an exemplary LCD device according to thepresent invention;

FIGS. 10A to 10C are cross sectional views of an exemplary first maskprocess of a method of fabricating an LCD device according to thepresent invention;

FIGS. 11A to 11C are cross sectional views of an exemplary second maskprocess of a method of fabricating an LCD device according to thepresent invention;

FIGS. 12A to 12D are cross sectional views of an exemplary third maskprocess of a method of fabricating an LCD device according to thepresent invention;

FIGS. 13A to 13E are cross sectional views of another exemplary thirdmask process of a method of fabricating an LCD device according to thepresent invention; and

FIG. 14 is a cross sectional view of an exemplary storage capacitoraccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings.

FIG. 4 is a plan view of an exemplary TFT array substrate according tothe present invention, and FIG. 5 is a cross sectional view along II-II′of FIG. 5 according to the present invention. In FIGS. 4 and 5, a TFTarray substrate may include a gate line 52 and a data line 58 crossingeach other, with a gate insulating pattern 90 therebetween, formed on alower substrate 88, a TFT 80 formed at each crossing of the gate anddata lines 52 and 58, a pixel electrode 72 within a pixel region definedby the crossing of the gate and data lines 52 and 58. Furthermore, theTFT array substrate may include a storage capacitor 78 formed at anoverlapped portion between a pre-stage gate line 52 and a storageelectrode 66 connected to the pixel electrode 72, a gate pad part 82connected to the gate line 52, and a data pad part 84 connected to thedata line 58.

The TFT 80 may include a gate electrode 54 connected to the gate line52, a source electrode 60 connected to the data line 58, a drainelectrode 62 connected to the pixel electrode 72, and a semiconductorpattern 147 including an active layer 92 overlapping the gate electrode54, with the gate insulating pattern 90 positioned therebetween, therebyforming a channel 70 between the source electrode 60 and the drainelectrode 62. The TFT 80 may respond to a gate signal supplied to thegate line 52 to allow the pixel electrode 72 to become charged, and thenmaintain a pixel voltage signal supplied to the data line 58.

The semiconductor pattern 147 may include the active layer 92 having thechannel portion between the source electrode 60 and the drain electrode62. The active layer 92 may be overlapped with the source electrode 60,the drain electrode 62, the data line 58, and a lower data pad electrode64. In addition, the active layer 92 may overlap with the storageelectrode 66, and may be formed to partially overlap with the gate line52 with the gate insulating pattern 90 positioned therebetween. Thesemiconductor pattern 147 may include an ohmic contact layer 94 formedon the active layer 92 for making ohmic contact with the sourceelectrode 60, the drain electrode 62, the storage electrode 66, the dataline 58, and the lower data pad electrode 64.

The pixel electrode 72 may be connected to the drain electrode 62 of theTFT 80 exposed to the exterior by a passivation film pattern 98, and maybe formed on the gate insulating pattern 90 of the pixel region exposedto the exterior by a passivation film pattern 98. The pixel electrode 72may generate a potential difference between a common electrode formed onan upper substrate (not shown) by a charged pixel voltage. According tothe potential difference, the liquid crystal material located betweenthe TFT substrate and the upper substrate (not shown) may rotate due todielectric anisotropy of the liquid crystal material and may cause lightincident through the pixel electrode 72 from a light source (not shown)to be transmitted to the upper substrate (not shown).

In FIG. 5, the storage capacitor 78 may include a pre-stage gate line 52and the storage electrode 66, wherein the storage electrode 66 may beoverlapped with the pre-stage gate line 52 with the gate insulatingpattern 90, the active layer 92, and the ohmic contact layer 94therebetween. Herein, the pixel electrode 72 may be connected to thestorage electrode 66 exposed to the exterior by the passivation filmpattern 98. The storage capacitor 78 causes the pixel voltage charged tothe pixel electrode 72 to be stably maintained until a subsequent pixelvoltage is charged.

The gate line 52 may be connected to a gate driver (not shown) throughthe gate pad part 82. The gate pad part 82 may include a lower gate padelectrode 56 extending from the gate line 52, and an upper gate padelectrode 74 connected on the lower gate pad electrode 56.

The data line 58 may be connected to a data driver (not shown) through adata pad part 84. The data pad part 84 may include a lower data padelectrode 64 extending from the data line 58, and an upper data padelectrode 76 connected on the lower data pad electrode 64. Furthermore,the data pad part 84 may include the gate insulating pattern 90, theactive layer 92, and the ohmic contact layer 94 formed between the lowerdata pad electrode 64 and the lower substrate 88.

The gate insulating pattern 90 may be formed in a region adjacent to theregion where the gate pad part 82 may be formed, and the passivationfilm pattern 98 may be formed within a region where the pixel electrode72, the upper gate pad electrode 74, and the upper data pad electrode 76may not be formed.

The TFT array substrate having such an arrangement may be fabricatedusing a three-round mask process. The three-round mask process mayinclude a first mask process for forming the gate patterns, a secondmask process for forming the semiconductor pattern and the source/drainpattern, and a third mask process for forming the gate insulatingpattern 90, the passivation film pattern 98, and the transparentelectrode pattern.

FIGS. 6A and 6B are plan and cross sectional views, respectively, of anexemplary first mask process of a method of fabricating a TFT arraysubstrate according to the present invention. In FIGS. 6A and 6B, a gatemetal layer may be formed by a deposition method, such as a sputtering,onto the lower substrate 88. Subsequently, the gate metal layer may bepatterned through a photolithography process using the first mask and anetching process to form the gate patterns including the gate line 52 andthe gate electrode 54. As the gate metal, Cr, MoW, Cr/Al, Cu, Al(Nd),Mo/Al, Mo/Al(Nd), Cr/Al(Nd) or the like may be used in a single layerstructure or a double layer structure.

FIGS. 7A to 7C are a plan view and sectional views, respectively, of anexemplary second mask process of a method of fabricating a TFT arraysubstrate according to the present invention. In FIG. 7B, a gateinsulating layer 90 a, an amorphous silicon layer 92 a, an n⁺ amorphoussilicon layer 94 a, and a source/drain metal layer 58 a may besequentially formed on the lower substrate 88 having the gate patternsby a deposition technique, such as plasma enhanced chemical vapordeposition (PECVD) and a sputtering method. Herein, the gate insulatinglayer 90 a may be made of an inorganic insulating material, such assilicon oxide (SiO_(x)) or silicon nitride (SiN_(x)). The source/drainmetal layer may be made of a molybdenum (Mo), a titanium (Ti), tantalum(Ta), and Mo alloy or the like.

Then, a photo-resist pattern 71 b may be formed through aphotolithography process using the second mask, as shown in FIG. 7B. Inthis case, a diffractive exposure mask having a diffractive exposingpart may be used as a second mask wherein the diffractive exposing partmay be corresponding to a channel portion of the thin film transistor.Accordingly, a photo-resist pattern 71 b of the channel portion may havea lower height than a photo-resist pattern of the source/drain patternpart. Subsequently, the source/drain metal layer may be patterned by awet etching process using the photo-resist pattern 71 b to providesource/drain patterns including the data line 58, the source electrode60, the drain electrode 62, which may be integral with the sourceelectrode 60, and the storage electrode 66, as shown in FIG. 7C.

Next, the amorphous silicon layer and the n⁺ amorphous silicon layer maybe simultaneously patterned by a dry etching process using the samephoto-resist pattern 71 b to provide the ohmic contact layer 94 and theactive layer 92. In addition, the photo-resist pattern 71 b, which mayhave a relatively low height in the channel portion, may be removed byan ashing process, and thereafter the source/drain pattern and the ohmiccontact layer 94 of the channel portion may be etched by a dry etchingprocess. Accordingly, the active layer 92 of the channel portion may beexposed to separate the source electrode 60 from the drain electrode 62.Then, a remainder of the photo-resist pattern 71 b left on thesource/drain pattern part may be removed using a stripping process.

FIGS. 8A to 8D are a plan view and cross sectional views, respectively,of an exemplary third mask process of a method of fabricating a TFTarray substrate according to the present invention. In FIGS. 8A to 8D, apassivation film 98, made of an inorganic insulating material, such assilicon oxide (SiO_(x)) and silicon nitride (SiN_(x)) or an organicinsulating material having a small dielectric constant, such as anacrylic organic compound, an organic insulating material, such asbenzocyclobutene (BCB) or perfluorocyclobutane (PFCB), may be entirelydeposited by a deposition technique, such as a sputtering, on the gateinsulating film 90 having the source/drain patterns formed thereon. Inaddition, a photo-resist may be entirely applied to the passivation film98. Subsequently, a photo-resist pattern 71 c may be formed by aphotolithography process using the third mask, i.e. a diffractiveexposure mask having a diffractive exposure part. Thus, the photo-resistpattern 71 c may be formed at a region besides the region upon which thegate pad may be formed, as shown in FIG. 8B. In addition, thephoto-resist patterns 71 c at a partial region P1 of the drain electrodeand the storage electrode, a pixel region P1, and a data pad region P1,which correspond to the diffractive exposure part, may be formed with aheight lower than that of a region P2, i.e., a shielding region, whichcorresponds to the diffractive exposure part. Subsequently, thepassivation film of the gate pad part 82 and the gate insulating film 90a of the passivation film may be removed by an etching process using thephoto-resist pattern 71C as a mask. Then, the photo-resist pattern 71 chaving a relatively lower height may be removed by an ashing process.Next, the passivation film may be patterned by an etching process usinga remainder of photo-resist pattern 71 c as a mask to expose a portionof the storage electrode 66, a portion of the drain electrode 62, andthe lower data pad electrode 64.

In FIG. 8C, a transparent electrode material 74 a may be entirelydeposited on the TFT array substrate 88 having the remainder ofphoto-resist pattern 71 c (in FIG. 8B) thereon by a depositiontechnique, such as a sputtering. Accordingly, the transparent electrodematerial may be made of indium-tin-oxide (ITO), tin-oxide (TO), orindium-zinc-oxide (IZO). Next, the photo-resist pattern 71 c may beremoved from the TFT array substrate 88 having the transparent electrodematerial deposited thereon by a stripping process, such as a lift-offmethod. Then, the transparent electrode material 74 a deposited on thephoto-resist pattern 71 c may be removed together with the photo-resistpattern 71 c being taken off to form a transparent pattern including theupper gate pad electrode 74, the pixel electrode 72, and the upper datapad electrode 76, as shown in FIG. 8D.

The upper gate pad electrode 74 may be formed to cover the lower gatepad electrode 56. In addition, the pixel electrode 72 may be connectedto the drain electrode 62 of the TFT 80 and the storage electrode 66 ofthe storage capacitor 78, and the upper data pad electrode 76 may beelectrically connected to the lower data pad electrode 64.

According to the present invention, a TFT array substrate and a methodof fabricating a TFT array substrate may adopt a first mask process forforming gate patterns, a second mask process for forming a semiconductorpattern and source/drain patterns, and a third mask process for forminga transparent electrode pattern by patterning the transparent electrodethrough a stripping process for a photo-resist pattern used in apatterning process for a gate insulating film and a passivation film.Accordingly, simplification of the TFT array substrate and fabricationprocess thereof may be achieved, thereby reducing fabrication costs andincreasing fabrication yield.

According to the present invention, a diffractive exposure mask may beused to fabricate a TFT array substrate by adopting the three-round maskprocess, wherein a gate insulating pattern having highest height amongthe TFT array may be formed between the pixel electrode and a lowersubstrate. Accordingly, a step height between the pixel regions havingthe pixel electrode formed thereon, a TFT, and a storage capacitor maynot be large. Thus, it is possible to maintain the same uniformity of arubbing process and the same contrast using a four-round mask processand a fifth-round mask process.

FIG. 9 is a plan view of an exemplary LCD device according to thepresent invention. In FIG. 9, each pixel on a TFT array substrate withan N×M matrix configuration of pixels may include a TFT defined at eachcrossing of a gate line 101, which may receive a scan signal from anexternal driving circuit, and a data line 103, which may receive animage signal. The TFT may include a gate electrode 101 a connected tothe gate line 101, an active layer 105 a overlapping the gate electrode101 a to be insulated from the gate electrode 101 a, and source/drainelectrodes 102 a and 102 b formed on the active layer 105 a. Inaddition, a pixel electrode 107 may be formed at a display region of thepixel, wherein the drain electrode 102 b may be connected to the pixelelectrode 107 to which the image signal may be supplied via the dataline 103 and the source/drain electrodes 102 a and 102 b. Furthermore,the pixel electrode 107 may be connected to a storage electrode 109overlapping the gate line 101. Moreover, the storage electrode 109 mayform the storage capacitor Cst along with the gate line 101, and thestorage capacitor Cst may be formed by overlapping the pixel electrode107 and the gate line 101 without forming the storage electrode 109.Although not shown, a repair pattern may be formed at a lower portion ofthe data line 103 and the repair pattern may be made in a process forforming the gate line.

Accordingly, an LCD panel may include the TFT array substrate, asdescribed above, wherein the drain electrode 102 b of the TFT may beelectrically connected to the pixel electrode 107 formed in the pixel sothat a liquid crystal material may be driven by applying a signal viathe source/drain electrodes 102 a and 102 b to the pixel electrode 107to display images. Although not shown, a gate pad and a data pad may beformed at extended one sides from the gate line 101 and the data line103 to receive signals from the external driving circuit, respectively.According to the present invention, a TFT array substrate constituted asdescribed above may be fabricated using a three-round mask process.

FIGS. 10A to 10C are cross sectional views of an exemplary first maskprocess of a method of fabricating an LCD device according to thepresent invention. In FIGS. 10A to 10C, a TFT region T, a storagecapacitor region S, a gate pad region G.P may be formed at one side of agate line, and a data pad region D.P formed at one side of a data line.

In FIG. 10A, after preparing a transparent substrate 110, aluminum (Al),medium (Mo), copper (Cu), MoW, MoTa, MoNb, chrome (Cr), tungsten (W), ora first metal film (not shown) of a double layer of aluminum (Al) andmolybdenum (Mo) may be deposited on the substrate 110 by a sputteringmethod. Then, the first metal film may be patterned through a first maskprocess to form the gate electrode 101 a, the gate line 101, and thegate pad 101 b.

FIG. 10B, an inorganic material, such as silicon nitride SiNx or siliconoxide SiOx, may be deposited along an entire surface of the substrate110 provided with the gate electrode 101 a, the gate line 101, and thegate pad 101 b to form a first insulating film 102, i.e., a gateinsulating film. Then, an amorphous silicon layer, an n⁺ amorphoussilicon layer doped with an impurity, such as phosphorus (P), and asecond metal film, such as Al, AlNd, Cr, Mo and Cu, may be sequentiallydeposited on an upper portion of the first insulating film 102. Next, asemiconductor layer 105 including the active layer 105 a and an ohmiccontact layer 105 b, source/drain electrodes 102 a and 102 b separatedby a designated gap from each other on an upper portion of thesemiconductor layer 105 to expose a middle of the active layer 105 a,the storage electrode 109 located at an upper portion of the gate line101, and the data pad 103 a may be respectively formed through a secondmask process.

Accordingly, the second mask process may employ a diffractive exposuremask or a half-tone mask, each of which may be a partial exposure mask,since the semiconductor layer 105 and the source/drain electrodes 102 aand 102 b are to be simultaneously formed through a single mask process.Such a diffractive exposure mask has a diffractive exposure region witha slit structure wherein an amount of exposure light irradiated throughthe diffractive exposure region is less than an amount of an exposurelight transmitted through a transmission region entirely transmittingthe light. Thus, after applying a photo-resist (PR) film, if the PR filmis partially exposed through the use of a mask provided with adiffractive exposure region and a transmission region, then a remainderof the PR film corresponding to the diffractive exposure region and aremainder of the PR film corresponding to the transmission region mayhave different heights from each other. In other words, for a positivePR film, the PR film where light is irradiated through the diffractiveexposure region has a thickness thicker than that of the transmissionregion. On the other hand, for a negative PR film, the PR film remainedat the transmission region is thickly formed.

According to the present invention, the semiconductor layer 105 and thesource/drain electrodes 102 a and 102 b may be simultaneously formedusing a characteristic of the diffractive exposure mask. In addition oralternatively, a half-tone mask may also be used. In a case of thehalf-tone mask, chrome (cr) may be formed at a shielding region andmolybdenum silicide (MoSi) may be formed at a half-tone region. Thus,the amount of light transmission may be controlled by adjusting athickness of the molybdenum silicide (MoSi).

FIGS. 11A to 11C are cross sectional views of an exemplary second maskprocess of a method of fabricating an LCD device according to thepresent invention. In FIG. 11A, a first insulating film 102, anamorphous silicon layer 105 a′, an n⁺ amorphous silicon layer 105 b′,and a second metal film 103′ may be sequentially stacked along an entiresurface of the substrate 110 provided with the gate electrode 101 a, thegate line 101, and the gate pad 11 b. Then, a PR film 130 may be appliedto an upper portion of the second metal film 103′, and light, such asultra violet, may be irradiated through a diffractive exposure mask 140.At this time, the diffractive exposure mask may include a diffractiveexposure region A1 partially transmitting the irradiated light, atransmission region A2 entirely transmitting the irradiated light, and ashielding region A3 entirely shielding the irradiated light.Accordingly, the light transmitted through the diffractive exposure mask140 may be irradiated onto the PR film 130.

In FIG. 11B, the PR film 130 exposed by the light may be developedthrough the diffractive exposing mask 140. Accordingly, the PR filmremains at only a region to which the light is irradiated through thediffractive exposure region A1 and the transmission region A2, and theremaining PR films at the other regions may be removed. Thus, a first PRpattern 130 a formed through the diffractive exposure region A1 may bethinner than a second PR pattern 130 b formed through the transmissionregion A2 due to use of the negative PR film. Since the negative PR filmhas a resolution higher than that of the positive PR film, the negativePR film may be used. Alternatively, the positive PR film may be used,wherein the pattern of the diffractive exposure mask may be oppositelymade. In other words, the light should be shielded at a region desiredto retain the PR film.

Next, the second metal film 103′, the n⁺ amorphous silicon layer 105 b,and an amorphous silicon layer 105 a formed at a lower portion of thefirst and the second PR patterns 130 a and 130 b may be etched by usingthe first and the second PR patterns 130 a and 130 b as masks to form anactive layer 105 a, an ohmic contact layer 105 b, a storage electrode109, and a data pad 103 a. Accordingly, a lateral surface portion of thedata pad 103 a may be exposed by a contact hole 103 a′.

In FIG. 11C, the first PR pattern 130 a may be removed through an ashingprocess. At this time, a portion of the second PR pattern 130 b may beremoved together with the first PR pattern to reduce a thickness of thesecond PR pattern. Then, the second metal film 103′ and the ohmiccontact layer 105 b may be exposed by removing the first PR pattern 130a through the use of the second PR pattern 130 b as a mask. Next, theymay be then etched to form the source/drain electrodes 102 a and 102 b.Accordingly, the source/drain electrodes 102 a and 102 b may beseparated from each other by a designate gap on an upper portion of theactive layer 105 a. Then, the ohmic contact layer 105 b may be formed inorder for reducing a contact resistance between the active layer 105 aand the source/drain electrodes 102 a and 102 b to smoothly transmitoperational signals. Next, the second PR pattern 130 b formed on thesource/drain electrodes 102 a and 102 b and the storage electrode 109may be removed by using a stripper.

FIGS. 12A to 12D are cross sectional views of an exemplary third maskprocess of a method of fabricating an LCD device according to thepresent invention. As described above, the semiconductor layer 105, thesource/drain electrodes 102 a and 102 b, the storage electrode 109, andthe data pad 103 a may be formed through the second mask process, andthen a second insulating film 106 (i.e., a passivation film) may beformed on their upper portion, as shown in FIG. 12A. After applying a PRfilm on the second insulating film 106, the PR film may be patternedthrough a third mask process, so that portions of the drain electrode102 b and the storage electrode 109 (in FIG. 12B) may be exposed to formfirst and second contact holes 101 b′ and 103 a′, respectively, exposingthe gate pad 101 b and the data pad 103 a. Then, a transparentconductive film may be deposited on the substrate 110 after the thirdmask process.

Next, a pixel electrode 107, which may be connected to the drainelectrode 102 b and the storage electrode 109, and a gate connectionterminal 101 c and a data connection terminal 103 b, respectively, maybe connected via the first and the second contact holes 101 b′ and 103a′ to the gate pad 101 b and the data pad 103 a, which may be formedthrough a lift-off process.

According to the present invention, by using the lift-off process in thethird mask process, the passivation film and the pixel electrode may beformed through a single mask process.

In FIG. 12A, an inorganic film, such as silicon oxide SiOx and siliconnitride SiNx, or an organic film such as BCB and acryl, may be appliedalong an entire surface of the substrate 110 provided with thesource/drain electrodes 102 a and 102 b, and the storage electrode 109(in FIG. 12B) to form a second insulating film 106. Then, a PR film maybe applied to an upper portion of the second insulating film, andpatterned through the third mask process to selectively form a PRpattern 105 a on the second insulating film 106.

In FIG. 12B, the first and the second insulating films 102 and 106 maybe removed by using the PR pattern 150 a as a mask to expose one side ofthe drain electrode 102 b and one side of the storage electrode 109 and,at the same time, to reveal the substrate 110 of a pixel region.Accordingly, the first contact hole 101 b′ exposing a portion of a gatepad 101 b and the second contact hole 103 a′ exposing a portion of adata pad 103 a may be formed together. Then, the first and the secondinsulating films 102 and 106 may be effectively removed by a dryetching. If the etching process continually progresses after forming allof the desired patterns, then the second insulating film 106 may be overetched to protrude an edge region of the PR pattern 150 a.

In FIG. 12C, a transparent conductive film 107, such as indium-tin-oxide(ITO) or indium-zinc-oxide (IZO), may be deposited along an entiresurface of the substrate 110 including the PR pattern 150 a having theprotruded edge region. At this time, since the conductive film 107′ maynot be deposited on a lower portion of the edge region in the PR pattern150 a, this region may be exposed to an exterior.

In FIG. 12D, the PR pattern 150 a having the partially exposed edgeregion may be removed by a stripper and, at the same time, theconductive film 107′ deposited on the PR pattern 150 a may also beremoved together therewith to form the pixel electrode 107, the gateconnection terminal 101 c, and the data connection terminal.Accordingly, the pixel electrode 107 may be connected to the drainelectrode 102 b and the storage electrode 109, the gate connectionterminal 101 c may be connected via the first contact hole 101 b′ to thegate pad 101 b, and the data connection terminal 103 b may be connectedvia the second contact hole 103 a′ to the data pad 103 a.

According to the present invention, in the third mask process, afterforming the PR pattern on the passivation film, the passivation film maybe over etched to form a protruded region of the PR pattern. Then, atransparent conductive film may be deposited on an upper portion of theprotruded region of the PR pattern to expose a portion of the PR patternto an exterior. Furthermore, the passivation film and the pixelelectrode may be formed by a single mask process through a lift-offprocess removing the PR pattern along with the transparent conductivefilm deposited on the upper portion of the PR pattern by a stripper.

In FIG. 12D, since step heights of the pixel electrode connected to thedrain electrode 102 b and the pixel electrode connected to the storageelectrode 109 are generated by the gate insulating film 102, the activelayer 105 a, the ohmic contact layer 105 b, and the drain electrode 102b, then liquid crystal material may not be normally driven at a regionof the step heights D and a defect, such as a light leakage, may occuron a display screen. Accordingly, in order to shield the region definedby the light leakage, a black matrix may be formed to extend to thelight leakage region. Accordingly, however, an aperture ratio may bereduced. As a result, there occurs a problem that screen brightness maybe reduced.

Therefore, according to the present invention, a diffractive exposuremask or a half-tone mask may be used during the third mask process toreduce the step heights of the pixel electrode produced at the regionsconnected to the drain electrode and the storage electrode, therebyminimizing the light leakage region and improving aperture ratio. Inother words, a diffractive exposure may be applied to the pixel regionto leave the gate insulating film without removing. As a result, thestepper heights due to the gate insulating film can be removed.

FIGS. 13A to 13E are cross sectional views of another exemplary thirdmask process of a method of fabricating an LCD device according to thepresent invention. Since FIGS. 13A to 13E are similar to FIGS. 12A to12D, description for configurations of shown in FIGS. 13A to 13E havebeen omitted for the sake of simplicity.

In FIG. 13A, an inorganic film, such as silicon oxide SiOx and siliconnitride SiNx, or an organic film, such as BCB or acryl, may be appliedalong an entire surface of a substrate 210 provided with source/drainelectrodes 202 a and 202 b, and a storage electrode 209 to form a secondinsulating film 206. Then, a PR film 250 may be applied to an upperportion of the second insulating film, and light, such as ultra violetlight, may be irradiated through a diffractive exposure mask or ahalf-tone mask 240. The diffractive exposure mask 240 may include adiffractive exposure region partially transmitting the light, atransmission region entirely transmitting the light, and a shieldingregion entirely shielding the light. Accordingly, the light transmittingthe diffractive exposure mask 240 may be irradiated to a PR film 250.

In FIG. 13B, the PR film 250 exposed by the light may be developedthrough the diffractive exposing mask 240. Then, the PR film may beretained at only a region to which the light is irradiated through thediffractive exposure region A1 and the transmission region A2, and theremaining PR films at the other region may be removed. Accordingly, athickness of a first PR pattern 250 a formed through the diffractiveexposure region A1 may be reduced to be less than a thickness of asecond PR pattern 250 b formed through the transmission region A2. Next,the first and the second insulating films 202 and 206 may be etched byusing the first and the second PR pattern 250 a and 250 b as masks toform a first contact hole 201 b′ exposing a gate pad 201 b and a secondcontact hole 203 a′ exposing a data pad 203 b. Then, the first and thesecond insulating films 202 and 206 may be efficiently removed by dryetching.

In FIG. 13C, the first PR pattern 250 a may be removed through an ashingprocess. Accordingly, a portion of the second PR pattern 250 b may alsobe removed to reduce a thickness of the second PR pattern. Then, thesecond insulating film 206 of the pixel region exposed by removing thefirst PR pattern 250 a may be etched by the second PR pattern 250 b usedas a mask to expose a portion of the drain electrode 202 b and a portionof the storage electrode 209 and, at the same time, to reveal the firstinsulating film 202 of the pixel region. At this time, the secondinsulating film 206 may be efficiently removed by dry etching. Inaddition, the etching process may continually progress after forming allof the desired patterns so that the second insulating film 206 may beover etched to protrude an edge region of the second PR pattern 250 a.

In FIG. 13D, a transparent conductive film 207′, such asindium-tin-oxide (ITO) or indium-zinc-oxide (IZO), may be depositedalong an entire surface of the substrate 210 including the second PRpattern 250 a in which the edge region may protrude. Since theconductive film 207′ may not be deposited on a lower portion of the edgeregion in the PR pattern 250 a, this region may be exposed to anexterior. Subsequently, the second PR pattern 250 a in which the edgeregion is partially exposed may be removed by a stripper and, at thesame time, the conductive film 207′ deposited on the second PR pattern250 a may also be removed together therewith to respectively form thepixel electrode 207 connected to the drain electrode 202 b and thestorage electrode 209 formed on the first insulating film 202 (i.e. thegate insulating film), as shown in FIG. 13E. Accordingly, a gateconnection terminal 201 c connected via the first contact hole 201 b′ tothe gate pad 201 b, and a data connection terminal 203 b connected viathe second contact hole 203 a′ to the data pad 203 a may besimultaneously formed.

In addition, step heights formed at regions at which the pixel electrode207 is connected to each of the drain electrode 202 b and the storageelectrode 209 may be formed due to the active layer 205 a, the ohmiccontact layer 205 b, and the drain electrode 202 b. Accordingly, thesize of the step heights may be reduced, as compared with the size ofthe step heights shown in FIG. 12D. In other words, in FIG. 12D, thestep heights of the pixel electrode 107 may be formed due to the gateinsulating film 102, the active layer 105 a, and the drain electrode 102b, whereas, in FIG. 13E, the pixel electrode 207 may be formed on thegate insulating film 202. Accordingly, the step heights due to the gateinsulating film 202 may be removed.

According to the present embodiment, sizes of step heights of a pixelelectrode may be reduced, thereby minimizing light leakage. In addition,since regions at which the light leakage is generated may be reduced, asize dedicated for forming a black matrix may be reduced, therebyimproving aperture ratio. Furthermore, a storage capacitor may be formedby overlapping the pixel electrode and a gate line without individuallyforming a storage electrode at a capacitor region.

FIG. 14 is a cross sectional view of an exemplary storage capacitoraccording to the present invention. In FIG. 14, a storage electrode maybe omitted and a gate line 201 may be overlapped with a pixel electrode207 with a gate insulating film 202 positioned therebetween to form astorage capacitor. Accordingly, when the storage capacitor is formed bydirectly overlapping the pixel electrode 207 with the gate line 201, itis possible to further efficiently reduce a step height of the pixelelectrode 207 made at the region of the storage capacitor. In otherwords, as shown in FIG. 13E, reduction of the step height of the pixelelectrode 207 was due to the storage electrode 209 and the semiconductorpattern (the active pattern and the n+ pattern) located at a lowerportion of the storage capacitor 209. However, according to the presentembodiment, since the storage electrode 209 is a factor resulting in thestep height, and may be removed, then aperture ratio may be improved.

According to the present invention, a TFT array substrate and a methodof fabricating a TFT array substrate may employ a three-round mask,thereby simplifying an arrangement of the substrate and fabricationprocess thereof. Thus, fabrication costs may be reduced and apertureratio may be improved.

According to the present invention, a diffractive exposure mask or ahalf-tone may be used during a process of forming a passivation film anda pixel electrode to reduce step heights produced at regions in whichthe pixel electrode is connected to a drain electrode and a storageelectrode. Thus, light leakage regions may be reduced and aperture ratiomay be improved.

According to the present invention, a transparent electrode formed on aPR pattern may be patterned by a stripping process for the PR patternused in a patterning process of a gate insulating film and a passivationfilm. Since the transparent electrode pattern may be formed using alift-off method, a total number of mask processes may be reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the TFT array substrate andmethod of fabricating a TFT array substrate of the present inventionwithout departing from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. A method of fabricating a thin film transistor array substrate,comprising: forming a gate pattern on a substrate, the gate patternincluding a gate electrode of a thin film transistor, a gate lineconnected to the gate electrode, and a lower gate pad electrodeconnected to the gate line; forming a gate insulating film on thesubstrate having the gate pattern; forming a source/drain patternincluding a source electrode and a drain electrode of the thin filmtransistor, a data line connected to the source electrode and a lowerdata pad electrode connected to the data line, and a semiconductorpattern formed beneath the source/drain pattern there along; and forminga transparent electrode pattern and a passivation film pattern stackedon remaining areas except for areas at which the transparent electrodepattern is formed, wherein the transparent electrode pattern includes apixel electrode directly contacting both the drain electrode and thesemiconductor pattern and formed on the gate insulating film, and thepixel electrode directly contacts an upper gate pad electrode and thelower gate pad electrode along sides of the upper and lower gate padelectrodes, and the pixel electrode directly contacts an upper data padelectrode and the lower data pad electrode along sides of the upper andlower data pad electrodes.
 2. The method according to claim 1, whereinthe step of forming the transparent electrode pattern and thepassivation film pattern includes: forming a passivation film on thesubstrate having the source/drain pattern formed thereon; forming aphoto-resist pattern having a step height on the passivation film;patterning the gate insulating film and the passivation film by usingthe photo-resist pattern to expose the lower gate pad electrode; ashingthe photo-resist pattern to expose the passivation film corresponding tothe pixel electrode and the upper data pad electrode; etching theexposed passivation film by using the ashed photo-resist pattern;depositing a transparent material on the substrate having a residualphoto-resist pattern; and removing the residual photo-resist pattern andthe transparent electrode material on the residual photo-resist patternto form a transparent electrode pattern.
 3. The method according toclaim 1, further comprising a storage capacitor including the gate lineand a storage electrode overlapping the gate line with the gateinsulating pattern and the semiconductor pattern positionedtherebetween.
 4. The method according to claim 3, wherein the step offorming the passivation film pattern includes partially exposing thedrain electrode and the storage electrode to be connected to the pixelelectrode.
 5. A method of fabricating a thin film transistor substrate,comprising: preparing a transparent substrate; depositing a first metalfilm on the substrate and then forming a gate line, a gate electrode anda gate pad through a first mask process; sequentially stacking a firstinsulating film, an amorphous silicon layer, an n⁺ amorphous siliconlayer and a second metal film on an entire surface of the substratehaving the gate electrode and the gate line, and forming a data linevertically crossing the gate line and defining a pixel region togetherwith the gate line, a semiconductor layer having an active layer and anohmic contact layer, a source/drain electrode, and a data pad through asecond mask process; and forming a second insulating film on an entiresurface of the substrate having the data line and the source/drainelectrode, exposing the first insulating film of the pixel region, thegate pad and the data pad through a third mask process, depositing atransparent conductive film on an upper portion of the first insulatingfilm, the gate pad and the data pad, to thereby form a pixel electrodedirectly contacting both the drain electrode and the ohmic contactlayer, directly contacting a gate connection terminal and the gate padalong sides of the gate connection terminal and gate pad, and directlycontacting a data connection terminal and the data pad along sides ofthe data connection terminal and data pad.
 6. The method according toclaim 5, wherein the second mask process includes: applying aphoto-resist film on the second metal film; irradiating light to thephoto-resist film through a mask having a partial exposure regionpartially transmitting the light and a transmission region entirelytransmitting the light and a shielding region shielding the light;developing the photo-resist film to which the light is irradiatedthrough the mask to form a photo-resist pattern on the second metalfilm, wherein the photo-resist pattern includes a first photo-resistpattern having a first thickness formed at the partial exposure regionand a second photo-resist pattern having a second thickness formed atthe transmission region; etching the amorphous silicon layer, the n+amorphous silicon layer and the second metal film by using the first andthe second photo-resist patterns as masks to form the data line, theactive layer, the ohmic contact layer and the data pad; removing thefirst photo-resist pattern to expose a middle region of the second metalfilm formed on the ohmic contact layer; and removing portions of thesecond metal film and the ohmic contact layer by using the secondphoto-resist pattern as a mask to form the source/drain electrode. 7.The method according to claim 6, wherein a molybdenum silicide (MoSi)film is formed at the partial exposure region of the mask, and achromium (Cr) film is formed at the shielding region.
 8. The methodaccording to claim 6, wherein the partial exposure region of the maskincludes a slit.
 9. The method according to claim 6, further comprisingforming a storage electrode at the time of the formation of thesource/drain electrodes, wherein the storage electrode overlaps the gateline to form a storage capacitor.
 10. The method according to claim 5,wherein the first thickness of the first photo-resist pattern is lessthan the second thickness of the second photo-resist pattern.
 11. Themethod according to claim 5, wherein the third mask process includes:applying a photo-resist film on the second metal film; irradiating lightto the photo-resist film through a mask having a partial exposure regionpartially transmitting the light, a transmission region entirelytransmitting the light, and a shielding region shielding the light;developing the photo-resist film to which light is irradiated throughthe mask to form a photo-resist pattern on the second metal film, thephoto-resist pattern including a first photo-resist pattern having afirst thickness formed at the partial exposure region and a secondphoto-resist pattern having a second thickness formed at thetransmission region; etching the first and the second insulating filmsby using the first and the second photo-resist patterns as masks to forma first contact hole exposing the gate pad and a second contact holeexposing a lateral surface of the data pad; removing the firstphoto-resist pattern; removing the second insulating film of the pixelregion by using the second photo-resist pattern as a mask to expose thefirst insulating film; depositing the transparent conductive film alongan entire surface of the substrate having the second photo-resistpattern, and removing the second photo-resist pattern and thetransparent conductive film formed on the second photo-resist pattern toform the pixel electrode, the gate connection terminal connected via thefirst contact hole to the gate pad, and the data connection terminalconnected via the second contact hole to the data pad.
 12. The methodaccording to claim 5, further comprising forming a repair pattern at alower portion of the data line.
 13. The method according to claim 12,wherein the repair pattern is formed along with the gate line during thefirst mask process.
 14. The method according to claim 5, wherein thetransparent conductive film is made of one of indium-tin oxide (ITO) andindium-zinc-oxide (IZO).
 15. The method according to claim 5, whereinthe pixel electrode is formed to be overlapped with the gate line.
 16. Amethod of fabricating a thin film transistor array substrate,comprising: preparing a transparent substrate; forming a gate line, agate electrode, and a gate pad on the substrate; forming a gateinsulating film along an entire surface of the substrate having the gateelectrode and the gate pad; forming a data line to vertically cross thegate line and defining a pixel region together with the gate line, asemiconductor layer having an active layer and an ohmic contact layer, asource/drain electrode, and a data pad, the data pad includes portionsof the semiconductor layer and the ohmic layer; exposing the gateinsulating film formed at each pixel region; forming a passivation filmalong an entire surface of the substrate having the data line and thesource/drain electrode; applying a photo-resist film to an upper portionof the passivation film; forming a photo-resist pattern on thepassivation film by using a mask; forming a contact hole exposing eachof the gate pad and the data pad by using the photo-resist pattern as amask for etching, and exposing the gate insulating film of the pixelregion; depositing a transparent conductive film along an entire surfaceof the substrate having the photo-resist pattern, the gate insulatingfilm of the pixel region and the contact hole; removing the photo-resistpattern and the transparent conductive film formed on the photo-resistpattern to form a pixel electrode directly contacting the gateinsulating film of the pixel region parallel to the entire surface ofthe substrate, and forming a gate connection terminal and a dataconnection terminal respectively connected via the contact hole to thegate pad and the data pad, the data connection terminal contacting theside regions of the portions of the semiconductor layer and the ohmiccontact layer of the data pad.
 17. The method according to claim 16,wherein the pixel electrode is formed to be overlapped with the gateline.
 18. The method according to claim 16, further comprising forming astorage electrode overlapping the gate line when the source/drainelectrodes are formed.
 19. The method according to claim 16, wherein thestep of forming the data line, the semiconductor pattern having theactive layer and the ohmic contact layer, the source/drain electrodes,and the data pad includes: sequentially stacking an amorphous siliconlayer, an n+ amorphous silicon layer, and a metal film on the gateinsulating film; applying a photo-resist film on the metal film;irradiating light to the photo-resist film through a mask, the maskhaving a partial exposure region partially transmitting the light and atransmission region entirely transmitting the light and a shieldingregion shielding the light; developing the photo-resist film to whichlight is irradiated through the mask to form a photo-resist pattern onthe metal film, the photo-resist pattern including a first photo-resistpattern having a first thickness formed at the partial exposure regionand a second photo-resist pattern having a second thickness formed atthe transmission region; etching the amorphous silicon layer, the n+amorphous silicon layer, and the metal film by using the first and thesecond photo-resist patterns as a mask to form the data line, the activelayer, the ohmic contact layer, and the data pad; removing the firstphoto-resist pattern to expose a middle region of the metal film formedon the ohmic contact layer; and removing a part of the metal film andthe ohmic contact layer by using the second photo-resist pattern as amask to form the source/drain electrodes.
 20. The method according toclaim 19, wherein the first thickness of the first photo-resist patternis less than the second thickness of the second photo-resist pattern.21. The method according to claim 16, wherein forming the photo-resistpattern on the passivation film includes: applying a photo-resist filmon the passivation film; irradiating light to the photo-resist filmthrough the mask, the mask having a partial exposure region partiallytransmitting the light and a transmission region entirely transmittingthe light and a shielding region shielding the light; developing thephoto-resist film to which light is irradiated through the mask to forma photo-resist pattern on the passivation film, the photo-resist patternincluding a first photo-resist pattern having a first thickness formedat the partial exposure region and a second photo-resist pattern havinga second thickness less than the first thickness formed at thetransmission region.
 22. The method according to claim 21, wherein aportion of the gate insulating film and a portion of the passivationfilm are etched by using the first and the second photo-resist patternsas masks to form contact holes for exposing the gate pad and the datapad, removing the first photo-resist pattern, and removing thepassivation film of the pixel region by using the second photo-resistpattern as a mask to expose the gate insulating film of the pixelregion.
 23. The method according to claim 22, wherein the firstphoto-resist pattern is removed through an ashing process.
 24. Themethod according to claim 21, wherein the photo-resist pattern includesthe second photo-resist pattern.